introduction

With the rapid development of technologies such as 5G, artificial intelligence, and high-performance computing (HPC), the semiconductor industry has increasingly stringent requirements for chip performance, integration, and energy efficiency. Hybrid bonding, as the core process of the next generation of advanced packaging, achieves high-density interconnection through direct bonding of metal and dielectric materials, effectively improving the performance and integration of CMOS image sensors, and becoming a key solution for 3D chip stacking and heterogeneous integration.

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一、 Principles and characteristics of Hybrid Bonding technology

Hybrid bonding is a technology that directly bonds chips or wafers through copper copper (Cu Cu) interconnects and dielectric materials (such as SiO ₂) in a one-step manner, achieving vertical connection without bumps and achieving high-density, low latency three-dimensional integration.

Hybrid bonding, as a revolutionary technology in the field of semiconductor packaging, has demonstrated significant advantages in improving chip performance, reducing power consumption, and achieving high-density integration.

1. High density interconnection

By directly bonding copper copper (Cu Cu), a smaller bonding pitch can be achieved, thereby increasing the interconnection density between chips and helping chips achieve 3D stacking and heterogeneous integration.

2. Low resistance and low latency

Direct copper interconnection reduces resistance caused by solder or oxide layers, effectively reducing signal transmission delay and improving chip speed.

3. High reliability and heat dissipation efficiency

Hybrid bonding has high bonding strength, with synchronous bonding between the dielectric layer and copper layer, resulting in higher reliability of the chip; The compact structure shortens the heat conduction path, effectively reduces the operating temperature of the chip, and further optimizes the heat dissipation performance efficiency.

二、 Market Application of Hybrid Bonding Technology

With the increasing maturity and cost reduction of Hybrid Bonding technology, it is expected to become the core driving force for semiconductor innovation in the post Moore era.

Hybrid Bonding technology is not only applied in 3D packaging, but also widely used in fields such as CMOS image sensors (CIS), 3D NAND, HBM, AI chips, etc.

CMOS Image Sensor: From Consumer Electronics to Industrial Vision

a) Back illuminated BSI upgrade: Using Hybrid Bonding technology, the pixel layer and logic layer are directly bonded, effectively improving dynamic range and reducing low light noise, providing ultra clear imaging for terminal applications such as smartphones, industrial cameras, and medical endoscopes.

b) Emerging application expansion: Hybrid Bonding technology can achieve 3D integration of storage units and logic circuits, promoting the application of high-resolution sensors in autonomous driving and medical imaging.

3D NAND Flash Memory: Improving Storage Efficiency and Speed

The competition for the number of layers in 3D NAND relies on Hybrid Bonding technology to break through physical limits. Hybrid Bonding replaces traditional TSV (silicon via) and achieves vertical stacking of storage cells and logic circuits, significantly improving read and write speed and effectively reducing power consumption.

High bandwidth memory (HBM): the key to breaking through stack limitations

High bandwidth memory (HBM) is the core component of AI chips and high-performance computing, and its stacking layers and interconnect density directly affect performance. Hybrid Bonding technology significantly enhances the stacking capability of HBM through bump free design and wafer level bonding. As a key technology iteration, HBM5 (fifth generation high bandwidth memory) requires Hybrid Bonding to meet performance requirements and break through the 16 layer stack limitation.

High performance computing (HPC) and AI chips: driving computing power upgrades

Against the backdrop of explosive growth in demand for AI computing power, the demand for computing power from AI big models has driven Hybrid Bonding technology to become the preferred solution for chip stacking. Hybrid Bonding can achieve efficient interconnection of multi chip systems through 3D stacking, playing an important role in AI chip systems such as drones, industrial robots, and other AI equipment fields.

三、 Changguang Yuanchen's technological development achievements in the field of Hybrid Bonding

As a semiconductor manufacturing enterprise specializing in the processing of CMOS image sensor wafers, Changguang Yuanchen has successfully overcome the 12 inch hybrid bonding process with outstanding technical strength and unremitting innovation spirit. Relying on our independently built advanced production line for CMOS image sensors, we have achieved the following main technical indicators:

1. 12 inch alignment accuracy: mean ≤ 100nm, 3 σ ≤ 500nm.

2. The bonding void rate is ≤ 1%.

3. Capable of Ta/TaN sputtering, Cu sputtering, Cu electroplating, Cu CMP, with Cu pillar discharge depth controlled within 10nm and Rq controlled within 0.5nm.

Changguang Yuanchen relies on its full chain process capabilities and advanced technical indicators to successfully build a 12 inch hybrid bonding process platform, which can quickly respond to customers' customized needs, support the verification, development, and mass production of image sensors such as BSI and 3D stacked CIS, meet the market's demand for high-performance image sensors, and help customers seize the technological high ground.